1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods of fabricating gate structures, such as gate electrodes.
2. Description of the Related Art
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon is then anisotropically etched selectively to the gate oxide, leaving a polysilicon gate electrode stacked on top of the gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed, usually by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.
The patterning of the polysilicon gate electrode entails masking the polysilicon layer with a resist and subsequently anisotropically etching the exposed portions of the polysilicon. The resist is patterned, that is, exposed and developed, into a shape that corresponds to the desired linewidth and floor plan of the polysilicon gate electrode defined by the anisotropic etch. Positive resists are frequently used, and may be of several different types, depending upon a number of parameters, such as the wavelength of illuminating radiation and the thickness of the polysilicon layer, to name a few. The poly gate mask is commonly patterned with a minimum lateral dimension or width corresponding to the minimum feature size or critical dimension ("CD") that may be patterned using the available microlithography technology.
With the resist in place, the polysilicon layer is anisotropically etched. The etch is usually carried out in a plasma ambient with ion bombardment. The etch consists of a main etch to remove the bulk of the exposed polysilicon and an overetch to catch any lingering polysilicon or etch by-products remaining. Endpoint detection for the main etch is frequently by emission spectroscopy, while the overetch is usually a timed process. A variety of etch chemistries are used to etch polysilicon. Most of these rely on fluorine-based molecules that, in conjunction with liberated resist particles, provide sidewall passivation during the etch.
The formation of a thin native oxide film on the exposed surfaces of the polysilicon gate electrode inevitably follows the gate etch process. The etch chamber will normally contain minute quantities of derelict oxygen, and may even contain large quantities where oxygen is used in the plasma ambient. The exposed silicon surfaces will readily react with oxygen present in the etch chamber. In many conventional processes, wafers are removed from vacuum following gate etch and stored for some period of time prior to additional processing. Native oxide will quickly grow on the exposed silicon surfaces after exposure to ambient air.
To ensure that the gate masking and etching processes produce a gate with a CD that falls within specifications, gate metrology measurements normally follow gate etch. The CD of the gate electrode determines, in large part, the electrical performance of the transistor. Accuracy in the linewidth measurement of gate CD's is therefore a vital aspect of reliably predicting the ultimate electrical behavior of the transistor. Unfortunately, native oxide film formation on the gate may lead to inaccurate determinations of gate CD. The problem stems from the fact that currently available metrology instruments will more often than not fail to discriminate oxide from polysilicon. As a result, the measured linewidth of the gate electrode will be greater than the actual linewidth of the gate electrode. The problem might be easily overcome if the thickness of the native oxide film were accurately known. In this circumstance, the true gate CD could be computed by subtracting twice the known thickness of the native oxide film. However, manufacturing experience has demonstrated that the formation of native oxide films on polysilicon gate electrodes exhibits a queue dependence that is difficult to predict. Thus, there is a high likelihood that a native oxide film will have grown to an unknown thickness at the time of linewidth measurement for the gate electrode.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.